Semiconductor devices, as represented by MOSFET devices that use silicon semiconductors, are integrated onto a single substrate and perform various functions, and thus have been used in a wide range of precision equipment, such as computers that are now a fundamental necessity of daily life. With the astonishingly rapid advancements in silicon semiconductor device technology, the demand exists for higher-performance and lower-cost integrated circuits.
Among such semiconductor devices, SOI transistors, which use an SOI substrate, have been attracting attention in recent years. SOI transistors are used particularly in compact, wireless equipment, such as cellular phones, and in portable computers. To accommodate the continuing demand for smaller size, lighter weight, lower power consumption and wireless network connections for such products, various sorts of SOI transistors have been researched and developed.
Using an SOI substrate is advantageous because it can reduce the entry of noise from digital circuits into analog circuits in a mixed digital/analog integrated circuit, which has been a problem to date. Because of this advantage, integrated circuits using an SOI substrate are expected to be applied mainly to mixed digital/analog integrated circuits incorporating a wireless circuit. For example, Japanese Unexamined Patent Publication No. 1998-256493 discloses a semiconductor device in which such an SOI substrate is used.
In an analog circuit for wireless communications, in addition to transistors, a number of other integrated circuit elements are required and should be fabricated on the SOI substrate, including high-resistive elements and a capacitor. A variable capacitance diode, used in the circuitry where wireless frequencies are controlled, is one such element.
In a conventional integrated circuit using a bulk substrate, a variable capacitance diode is formed vertically by optimizing the doping profile of impurities with an ion implantation technique, one example of which is shown in FIG. 10.
FIG. 10(a) is a cross-sectional view of a vertical variable capacitance diode used in a bulk substrate integrated circuit, and FIG. 10(b) is a diagram showing the doping profile along line I-J of FIG. 10(a). As shown in FIG. 10(a), in the vertical variable capacitance diode 52, an buried cathode (n+ region) 521, an n− region 522, and an anode (p+ region) 523 are formed in this order on a silicon substrate 51. Also, the doping profile of the phosphorus impurity within the n− region 522 is adjusted by means of an ion implantation technique, as described earlier, such that the dopant concentration decreases gradually from the anode 523 side toward the cathode 521 side, as shown in FIG. 10(b).
At the interface between the anode 523 and the n− region 522 in the variable capacitance diode 52, a pn junction is formed, which acts as a capacitor. Because the dopant concentration is adjusted as described above, a depletion layer 524 of the pn junction that acts as a capacitor spreads through most of the n− region 522. More specifically, the anode 523-side edge of the depletion layer 524 is located approximately in the vicinity of the interface between the n− region 522 and the anode 523, while the cathode 521-side edge of the depletion layer 524 is located near the center of the n− region 522. In FIG. 10(a), the cathode 521-side edge of the depletion layer 524 is indicated as depletion layer edge 524a. 
Generally, the junction capacitance C of a diode is expressed in the same way as that of a parallel-plate capacitor having two plates with surface area S, given by:C=∈0∈Si×S/d  (1)where d is the distance between the two parallel plates, which is equivalent to the width d of the depletion layer of the pn junction in FIG. 10(a), ∈0 is the dielectric constant in a vacuum, and ∈Si is the relative dielectric constant of silicon. When a semiconductor material other than silicon is used, the relative dielectric constant intrinsic to the material is applied instead.
Based on formula (1), when reverse bias voltage is applied to the pn junction, the width d of the depletion layer increases, and the capacitance C is reduced. This presents a problem in that, when the width d of the depletion layer is increased due to an increase in the reverse bias voltage, the change in the capacitance C is reduced accordingly, because the capacitance C varies in inverse proportion to the width d of the depletion layer.
As a solution to the above problem, the n− region 522 of the variable capacitance diode 52 is doped such that the dopant concentration decreases gradually, as shown in FIG. 10(b). Hence, as the width d of the depletion layer increases due to an increase in reverse bias voltage, the depletion layer edge 524a moves toward the region with a lower concentration of phosphorus, thereby enlarging the variation in the depletion layer 524. Consequently, a reduction in the capacitance change ratio due to an increase in reverse bias voltage is prevented.
However, a problem arises when attempting to form such a variable capacitance diode on an SOI substrate. A conventional device with a planar (horizontal) shape may be applied in its originally designed shape to an SOI integrated circuit in the same way as it is to a bulk substrate integrated circuit. However, a conventional device with a vertical shape, i.e., the variable capacitance diode described above, is very difficult to apply in its originally designed shape to an SOI integrated circuit in the same way as it is to a bulk substrate integrated circuit because the active silicon layer of the SOI substrate is thin.
One possible approach is to simply form the variable capacitance diode in a planar shape on an SOI substrate, an example of which is shown in FIG. 11. FIG. 11(a) is a plan view of a variable capacitance diode formed in a planar shape on a conventionally structured SOI substrate, and FIG. 11(b) is a cross-sectional structural view taken on line K-L of FIG. 11(a).
As shown in FIG. 11(b), an buried oxide film 62 is formed on the top of a silicon substrate 61 to electrically isolate the silicon substrate 61 from a silicon layer thereabove, in which the device, i.e., the variable capacitance diode 63, will be formed. The variable capacitance diode 63 formed on the buried oxide film 62 is composed of an anode (p+ region) 631, an n− region 632 and a cathode (n+ region) 633. Around the variable capacitance diode 63, a device isolation oxide film 64 is formed to electrically isolate the diode from other devices.
As shown in FIG. 11(a), the variable capacitance diode 63 has the overall shape of a rectangle, and comprises the rectangular anode 631 along one end thereof and the rectangular cathode 633 along the other end thereof. The rectangular n− region 632 is sandwiched between the anode 631 and the cathode 633, which are almost identical to each other in shape. In the variable capacitance diode 63, there are high concentrations of the p-type dopant in the anode 631 (e.g., boron or indium) and the n-type dopant in the cathode 633 (e.g., phosphorus or arsenic), while the concentration of the dopant in the n− region 632 (e.g., phosphorus or arsenic) is low.
At the interface between the anode 631 and the n− region 632 in the variable capacitance diode 63, a pn junction is formed, which will act as a capacitor, as in the case of the vertical variable capacitance diode described earlier. The anode 631-side edge of a depletion layer 634 is located substantially near the interface between the n− region 632 and the anode 631, while the cathode 633-side edge of the depletion layer 634, i.e., depletion layer edge 634a, is located near the center of the n− region 632.
However, a problem arises again when such a variable capacitance diode is simply implemented in a planar shape on an SOI substrate. In the variable capacitance diode formed in a planar shape shown in FIG. 11, it is very difficult to dope the n− region such that the dopant concentration decreases gradually from the anode side toward the cathode side in the horizontal direction as is done in the vertical variable capacitance diode. As a consequence, when the width d of the depletion layer is increased by an increase in reverse bias voltage, the change in the capacitance C is reduced accordingly, as specified by formula (1). The problem, therefore, is that when a conventional variable capacitance diode is simply fabricated in a planar shape on an SOI substrate, its capacitance change ratio is small, therefore failing to provide the performance desired for an analog circuit.
An object of the present invention is to solve the above-mentioned problems and provide a variable capacitance diode with a planar shape which is formed on an SOI substrate and which can prevent a reduction in the capacitance change ratio even when the applied reverse bias voltage is increased, and a process for manufacturing the same.